The present invention relates generally to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to performing a two stage anneal in the formation of an alloy interconnect.
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC. Nevertheless, there are many factors that make the continued miniaturization of ICs difficult. For example, as the size of interconnects or vias (pathways between integrated circuit layers used to electrically connect separate conductive layers) decreases, electrical resistance increases.
Conventional integrated circuits utilize vias or interconnects to connect structures (e.g., gates, drain regions, source regions) and conductive lines. For example, a via can connect a gate above the substrate to a conductor line in a metal 1 layer. Vias can also interconnect conductive lines. For example, a via can connect a conductive line in a metal 1 layer to a conductor line in a metal 2 layer. A via is typically a metal plug which extends through an insulative layer in a multilayer integrated circuit.
Vias and barrier layers are discussed in U.S. Pat. Nos. 5,646,448; 5,770,519; and 5,639,691; each of which are assigned to the assignee of the present application. A barrier layer can be used to protect the via and insulative layer from metal diffusion and the via and conductive line from electromigration (EM). The barrier layer can contribute significantly to resistance associated with the via metal. Electromigration is the mass transport due to momentum exchange between conducting electrons and diffusing metal atoms. Electromigration causes progressive damage to the metal conductors in an integrated circuit. In general, metals are most susceptible to electromigration at very high current density and temperatures of 100xc2x0 C. or more.
The performance of vias or interconnects can be enhanced with the use of alloys. For example, alloys, such as, tin (Sn), Zinc (Zn), indium (In), calcium (Ca), chromium (Cr), zirconium (Zr), hafnium (Hf), and lanthanum (La) can be distributed throughout a via. For example, alloys can be used to enhance the properties of a copper via. However, the alloys must be uniformly distributed for optimized performance. Nevertheless, it is a challenge to control copper grain growth and alloy doping distribution when forming copper alloy vias and trenches. In a single damascene structure, the alloy can be either in a trench or via or both. In a dual damascene structure, the alloy is in both a trend and via. It is particularly difficult to control alloy doping distribution if the copper alloy layer is introduced prior to copper grain growth. Copper grain growth can be important because large grain growth can provide better reliability and lower resistance.
Thus, there is a need to distribute alloy doping uniformly in a via and yet allow suitable copper grain growth. Further, there is a need to have large grain growth and uniformity of alloy doping distribution. Even further, there is a need to improve the formation of an alloy via or interconnect. Yet further, there is a need for a method of forming a via and/or trench which has uniform alloy distribution and large copper grain size.
An exemplary embodiment is related to a method of performing a two stage anneal in the formation of an alloy interconnect. The method can include forming a via and/or trench aperture in a dielectric layer, providing a seed layer along lateral side walls of the via aperture, rapid thermal annealing the seed layer to facilitate copper grain growth in the via, and slowly annealing the seed layer to facilitate desired distribution of alloy doping. The via aperture provides an area for the alloy interconnect.
Another exemplary embodiment is related to a method of forming a via in an integrated circuit fabrication process. The method can include providing a conductive layer over an integrated circuit substrate, and providing a barrier material at a bottom and sides of a via aperture in a dielectric layer positioned over the conductive layer to form a barrier layer separating the via aperture from the conductive layer. The method can also include depositing a seed layer over the barrier layer where the seed layer includes alloy elements, providing a rapid thermal anneal (RTA) or hot plate anneal to cause grain growth in a via material in the via aperture, and providing a slow anneal to distribute alloy elements uniformly in via material.
Another exemplary embodiment is related to a method of forming a via in an integrated circuit. This method can include depositing a conductive layer, depositing an etch stop layer over the conductive layer, depositing an insulating layer over the etch stop layer, forming an aperture in the insulating layer and the etch stop layer, providing a barrier material at a bottom and sides of the aperture to form a barrier material layer providing separation from the conductive layer, implanting at least one alloy element into an seed layer over the barrier material layer, filling the aperture with a via material to form a via, annealing the via to cause grain growth, and annealing the via to distribute at least portions of the at least one alloy element in the via.